Formal Semantics and Proof Techniques for Optimizing VHDL Models (1999)
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- Synopsis
- Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.
- Copyright:
- 1999
Book Details
- Book Quality:
- Publisher Quality
- ISBN-13:
- 9781461551232
- Related ISBNs:
- 9780792383758
- Publisher:
- Springer US
- Date of Addition:
- 01/16/21
- Copyrighted By:
- N/A
- Adult content:
- No
- Language:
- English
- Has Image Descriptions:
- No
- Categories:
- Nonfiction, Computers and Internet, Technology
- Submitted By:
- Bookshare Staff
- Usage Restrictions:
- This is a copyrighted book.
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